1. Field of the Invention
This invention relates to systems utilizing chargecoupled devices, and to the clocking circuits and systems used to control the operation of charge-coupled devices. The invention relates particularly to a dual clock logic system for charge-coupled device area image sensors.
2. Description of the Prior Art
Charge-coupled semiconductor devices were first invented by W. S. Boyle and G. E. Smith (see their paper, "Charge-Coupled Semiconductor Devices," Bell Systems Technical Journal, Vol. 49, Page 587, and U.S. Pat. No. 3,858,232). Since that time the development of charge-coupled devices (also referred to as CCD's) has been described in numerous publications. See, e.g., the article by Gilbert F. Amelio, "Charge-Coupled Devices," Scientific American, February 1974, Vol. 230, No. 2, at Page 23, and C. H. Sequin and M. F. Tompsett, Charge Transfer Devices, Academic Press, 1975. Charge-coupled devices have been used in numerous applications, for example, as memories, analog delay lines, and image sensors.
Information is processed in most CCD's by the use of transport or shift registers. These registers transfer and manipulate packets of charge, usually groups of electrons, representative of analog or digital information. The CCD ultimately produces an output signal for use or interpretation by a signal processing circuit. Examples of CCD's operating in the general manner described above are the Fairchild Camera and Instrument Corporation (herein Fairchild) products CCD 464, a 65k bit memory, and CCD 201, an area image sensor.
The process of electron transfer along a CCD shift register typically is controlled by a set of externally generated clock signals. Such clock signals also generally are required to control and synchronize associated circuits which detect, amplify, or otherwise process the information represented by the packets of electrons. The frequency of the clocking signals applied to the shift register determines the throughput rate for the particular device operation. Therefore, a number of these signals applied to the CCD will be at the information output rate, or bit-rate. Other signals, however, will be at lower frequencies. The specific relationship between the other signals and the bit-rate signals is determined by the particular CCD organization. For example, a signal applied to the transfer gate of a 256 element linear image sensor such as the Fairchild product CCD 110 will occur only once every 256 bit-rate signals. The transfer gate signal for the Fairchild product CCD 121, a 1728 linear image sensor, will occur at a much lower frequency, that is, only once every 1728 bit-rate signals.
It is well known in the CCD art that for low noise operation the bit-rate signals must be generated carefully, and with a high regard for noise content, because the bit-rate signals may inject noise directly into the information signal, that is, directly into the on-chip detector through capacitive coupling. Typical CCD systems of the past have utilized a single master clock oscillator, the frequency emanating from which was divided by logic counters to produce a bit-rate signal and further divided to produce other lower frequency signals. Unfortunately, this prior art approach invariably produced cross-talk between the bit-rate signals and the lower frequency signals due to the repetitive binary "footprint" of the counting process. The result was a bit-rate signal which contained repetitive digital noise, and therefore, introduced this noise into the information siganl.
In CCD area imaging applications certain factors have mandated the use of the above-described scheme in which logic circuits divide the frequency of a master clock oscillator to generate bit rate and lower frequency signals. For example, in a television compatible system where certain specified waveforms must be generated, a TV sync generator integrated circuit, such as Fairchild product 3262 is used to generate certain complex synchronization signals for display of video information. This approach, however, has been unsatisfactory as it substantially increases the amount of digital clock noise in the video signal. The periodic nature of the noise introduced by the counting circuits causes such noise to appear as a series of regularly spaced vertical lines across the face of the display apparatus, for example, a television monitor. This noise was distracting to anyone desiring to view the monitor, and reduced the resolution of the entire system.
Accordingly, it is an object of this invention to provide a system for generating bit-rate signal for CCD control in which the bit-rate frequency is generated independently of all other system timing signals. It is a further object of this invention that the bit-rate generator be in synchronization with the lower frequency clocking signals to maintain proper alignment of the displayed image.